Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Jungwoo | ko |
| dc.contributor.author | Na, Seonjin | ko |
| dc.contributor.author | Lee, SangHyeon | ko |
| dc.contributor.author | Lee, Sunho | ko |
| dc.contributor.author | Huh, Jaehyuk | ko |
| dc.date.accessioned | 2023-11-13T03:01:03Z | - |
| dc.date.available | 2023-11-13T03:01:03Z | - |
| dc.date.created | 2023-11-11 | - |
| dc.date.created | 2023-11-11 | - |
| dc.date.issued | 2023-10-30 | - |
| dc.identifier.citation | IEEE/ACM International Symposium on Microarchitecture | - |
| dc.identifier.uri | http://hdl.handle.net/10203/314503 | - |
| dc.language | English | - |
| dc.publisher | IEEE/ACM | - |
| dc.title | Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.citation.publicationname | IEEE/ACM International Symposium on Microarchitecture | - |
| dc.identifier.conferencecountry | CN | - |
| dc.identifier.conferencelocation | Toronto | - |
| dc.contributor.localauthor | Huh, Jaehyuk | - |
| dc.contributor.nonIdAuthor | Kim, Jungwoo | - |
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