The role of passivation layer during thermal annealing for oxide semiconductor thin films

Abstract

The change of the resistance of active films during thermal annealing was monitored under the split of passivation layers and active layers. ALD deposited Al2O3 layer and PECVD deposited SiO2 layer were applied for the passivation layer and sputter deposited Al-doped InZnSnO and InGaZnO were applied for the active layer. It is found that Al2O3 passivation layer supplies dopants to the active interface during high temperature annealing and the side wall of Al:IZTO pattern contains many defects, which become conductive during high temperature annealing through detailed measurement of resistance of patterned oxide semiconductor thin films with various sizes. It is suggested that PECVD deposited SiO2 layer with proper pretreatment (possibly N2O plasma treatment) will be best candidate for the passivation layer in the oxide TFTs, especially in the case of oxide TFTs with high mobility.