Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip

Abstract

A crossbar array that combines computation and storage functions in non-volatile resistive memory is a promising artificial intelligence (AI) computing architecture. It is because it can largely save a significant energy from interconnection between a processor and a memory. However, the parasitic components from its dense interconnection can affect the electrical performance of noise-sensitive analog-computing and small read voltage margin of the memristor. In this paper, we designed a large-scale memristor crossbar array, and modeled it into equivalent circuit models and analyzed its signal integrity considering IR drop, crosstalk and ripple. These factors were compared depending on the physical dimension of on-chip interconnection and operating frequency. Based on the eye-diagram simulation, we could successfully demonstrate the voltage margin and timing margin for memristor operations.