Loop unrolled SAR based two-step ADC with time-domain backend

Abstract

This work presents a Loop Unrolled SAR based Two-Step with Time-domain Backend which has less calibration burden. In proposed A, it achieves fast conversion speed (1GS/s) and low power consumption (1.74mW) by LU(Loop Unrolled)-SAR based Time-domain interpolating Flash. In case of conventional LU-SAR ADC and Flash ADC, offset calibration for mismatch error should be included. However, proposed A employs a single Voltage-to-Time converter(VTC) by employing pseudo LU-SAR in coarse stage and proposed time-domain interpolating Flash. Consequently, it eliminates need for offset calibration by utilizing a single VTC in proposed A architecture. In proposed B, it employs LU-SAR based backend Vernier time-domain Flash ADC. By replica structure between VTC and Vernier TDC(Time-domain converter), it reduce the calibration burden of offset mismatch and range alignment between voltage-domain and time-domain.