Package design for signal integrity of low-power double data rate memory

Abstract

As the data rate increases, signal distortion is intensified because of impedance mismatch in a data (DQ) channel of low-power double data rate (LPDDR) memory package. This paper presents a package design to reduce multiple reflection caused by impedance mismatched segments such as bonding wire, trace, and solder ball. Simulation is conducted for signal integrity (SI) analysis by using a package with two coupled lines. The simulated package model has the same dimension as the DQ channels of LPDDR5 dynamic random-access memory (DRAM) package. The structures of the bonding wire and reference plane above the solder ball are modified and the dielectric constant of the prepreg is changed to mitigate impedance mismatch. The effect of impedance mismatch mitigation and increased crosstalk is traded off. The conventional and proposed package designs are analyzed through EM simulation and transient simulation in the frequency domain and time domain. The SI performance of the proposed package design is evaluated and the data rate limit is confirmed through eye diagram simulation.