(A) study of 1T DRAM using buried double-well junction on a bulk-Si wafer

Abstract

As DRAM scaling continues, development becomes more difficult due to insufficient amount of capacitor charge and increased process difficulty. Therefore, although research on capacitor-less DRAM such as SOI has been actively conducted, the possibility of implementation is low due to economic feasibility and density problems. This paper presents the possibility of 1T DRAM through buried junction instead of SOI as 1T DRAM. The latch-up characteristics that can be sensed while maintaining the existing process and cell density were confirmed through measurement. In addition, it was confirmed that the level was equivalent to that of DRAM, and there was no specificity in terms of durability. In conclusion, I think that the characteristics of 1T DRAM using buried junction have been confirmed and suggested a new direction for capacitor-less DRAM.