Reliability and performance improvement techniques for counter caches in secure memories

Abstract

Secure memory is one of the hardware-based trusted execution environment techniques. It prevents unauthorized access and forgery of data transferring between the processor and main memory from an attacker and achieves this by guaranteeing confidentiality and integrity. Confidentiality can be achieved by encrypting data passing between the processor and memory. However, to satisfy the integrity, tree traversal must be performed for the integrity tree composed of counter nodes for every data access. A large amount of additional memory access causes significant performance degradation in this process. To mitigate this performance penalty, a counter cache is used that stores part of the counter nodes in the integrity tree. However, the counter cache introduces new reliability and performance issues that do not occur in traditional data caches. This dissertation proposes a reliability and performance improvement technique for the counter cache. In particular, we distinguish the difference between the traditional data cache and the counter cache and improve the reliability against the transient error and the efficiency of the counter cache based on the structural and operational characteristics of the counter cache. First, we analyze the new reliability issues caused by the counter cache and propose low-cost detection and recovery techniques. All counters in the counter node are propagated to lower nodes or data areas when a transient error occurs because all nodes are dependent on child nodes according to the inherent characteristics of the integrity tree. In addition, access to data in a wide area may become impossible depending on the logical level of the counter node in which the error has occurred. When a counter node is loaded in the counter cache, it is verified through a message authentication code (MAC). This MAC verification process can be used to detect and recover errors. In addition, we introduce a low-cost replicating method for vulnerable counters in the counter cache that cannot be recovered from an error. Second, we discuss counter cache allocation techniques that can increase the effectiveness of the counter cache. The counter cache loads 64-byte counter nodes from main memory which embed multiple counters. According to our observation, after a counter node is loaded into the counter cache, only a small amount of counters are accessed and then evicted from the cache again. This access pattern can be seen more frequently if the counter nodes are reside in the lower level of the integrity tree. In other words, most counters loaded into the counter cache are unused and cause space overheads. If these waste spaces can be eliminated, the utilization of the counter cache can be increased. Therefore, we propose a technique to increase the cache efficiency by loading only required counters into the counter cache. The proposed methods were evaluated through cycle-accurate simulators and selected memory-intensive workloads in various benchmarks. Through experiments, we demonstrate that the proposed methods based on the characteristics of secure memory can efficiently improve the reliability and performance of the counter cache.