Method for fabricating chip size packages using lamination process

Abstract

A method for fabricating chip size packages which uses a lamination process, thereby not only achieving an improvement in the reliability of final electronic products, a reduction in the manufacturing costs, and a mass production resulting in a high marketability, but also being applicable to the fabrication of packages for both memory and non-memory chips and enabling the final electronic products to have high electronic performance while making the package size of the final electronic products not greater than 1.2 times the semiconductor chip size. The method includes the steps of cutting a wafer into a plurality of wafer strips each having several dies, arranging the wafer strips on an adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another, bonding the aligned wafer strips to the polymer film in accordance with a lamination process, forming a polymer dam made of an epoxy-based polymer on the polymer film around a wafer region, forming an encapsulant encapsulating the wafer strips, forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method, forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming an array of I/O pads for the chips, fusing solder balls to the I/O pads, and cutting several ten dies integrally formed in one lot into separate packages.