(A) NAND flash-based deep neural network accelerator exploiting bit-level sparsity

Abstract

As data communication accounts for most of the energy consumption and the latency when running DNN applications, processing in-memory (PIM) approach that combines the role of the memory and the processor appears. However, previous works on the conventional memories DRAM and SRAM have a limitation of low energy-/area- efficiency. Meanwhile, NAND flash has not been considered as the proper platform for PIM due to its slow and less energy-efficient memory operation. Nevertheless, it has sufficient potential to solve the data communication issue effectively with its high-density and non-volatile properties. In this thesis, a NAND flash-based DNN accelerator, called S-FLASH, that utilizes the properties of NAND flash is proposed. This thesis targets to achieve both high energy efficiency and large area efficiency among various platforms to execute DNN applications. To achieve energy-efficient computation, firstly, a current-sum based computation by utilizing a string structure of NAND flash is implemented. Furthermore, the bit width of partial multiplication by considering the analog-to-digital converter (ADC) resource, which limits the overall energy efficiency and the throughput of the system, is optimized. Lastly, a massive number of zero partial multiplication results from the bit-level sparsity to enhance both energy efficiency and throughput is exploited. The evaluation results show that the proposed method which utilizes the bit-level sparsity maximally achieves 8.23× performance gain. Also, S-FLASH delivers 19.01×, 4.45× higher energy efficiency with 3.46×, 24.85× more on-chip capacity per area than an DRAM- or SRAM-based DNN accelerator, respectively.