High-speed and low-power VLSI design of global optical flow estimation method for mobile systems모바일 시스템을 위한 전역적 옵티컬 플로우 추정 방법의 고속 및 저전력 VLSI 설계

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Owing to the high complexity of the global optical flow estimation method, it is designed with a VLSI typically for real-time and low-power operation in mobile systems. Most VLSI designs for the global method focus on reducing the excessive external memory access caused by the global and iterative processes. However, to achieve this goal, considerable amounts of resources are used and the throughput is decreased. To address these issues, a multirow-based propagation approach and an efficient VLSI architecture are proposed in this dissertation. To compute the optical flow by using the small internal memory without external memory access, this approach divides an input image horizontally and vertically, and a subimage consisting of multiple rows is processed sequentially. Furthermore, to prevent the accuracy degradation that originates from the boundaries of the divided subimages, boundary conditions are imposed based on the smoothness of the optical flow, which is generally assumed in the global method. In addition, the main equations of the global optical flow method are simplified to boost the processing speed. The experimental results demonstrate that the external memory access is reduced by 96.55% with negligible accuracy degradation. Furthermore, the proposed design uses 80.4%-93.6% less internal memory and achieves 2.2$\times$-29.3$\times$ higher throughput-per-watt compared to state-of-the-art designs.
Advisors
Park, In-Cheolresearcher박인철researcherKyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2021
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2021.2,[iv, 60 p. :]

Keywords

global optical flow estimation▼amultirow-based propagation approach▼avery-large-scale integration (VLSI)▼afield-programmable gate array (FPGA)▼amobile system; 전역적 옵티컬 플로우 추정▼a다중행 기반 전파 방식▼a초고밀도 집적 회로(VLSI)▼a필드 프로그래머블 게이트 어레이(FPGA)▼a모바일 시스템

URI
http://hdl.handle.net/10203/295643
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=956644&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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