Improving the electrical performance of vertical thin-film transistor by engineering its back-channel interface

Abstract

This paper reports the effect of the properties of a back-channel region of a vertical thin-film transistor (VTFT) on its electrical performance. The deposition of a thin layer of SiO2 on a damaged back-channel region was found to improve the subthreshold swing (SS) from 0.25 to 0.12 V/dec, while maintaining the field-effect mobility. Detailed analysis of the surface morphology of the back-channel region revealed that the application of advanced photolithography resulted in a significantly smoother back-channel interface, yielding higher-performing VTFTs. The VTFT fabricated using a high-resolution, stepper photolithography system exhibited a linear mobility (mu(lin)) of 14.60 cm(2)/Vs, a saturation mobility (mu(sat)) of 23.69 cm(2)/Vs, and an SS value of 0.13 V/dec. Meanwhile, the VTFT fabricated using a standard projection aligner displayed mu lin, mu sat, and SS values of 5.74 cm(2)/V.s, 13.87 cm(2)/V.s, and 0.27 V/dec, respectively. These results revealed the electrical performance of the VTFT to be strongly influenced by the properties of the back-channel region.