DC Field | Value | Language |
---|---|---|
dc.contributor.author | Joo, Younghwan | ko |
dc.contributor.author | Yu, Yonggyun | ko |
dc.contributor.author | Jang, In Gwun | ko |
dc.date.accessioned | 2021-11-30T06:43:16Z | - |
dc.date.available | 2021-11-30T06:43:16Z | - |
dc.date.created | 2021-11-29 | - |
dc.date.created | 2021-11-29 | - |
dc.date.created | 2021-11-29 | - |
dc.date.created | 2021-11-29 | - |
dc.date.issued | 2021-11 | - |
dc.identifier.citation | IEEE ACCESS, v.9, pp.149766 - 149779 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | http://hdl.handle.net/10203/289690 | - |
dc.description.abstract | This study proposes a unit module-based acceleration method for 2-D topology optimization. For the purpose, the first-stage topology optimization is performed until the predefined iteration. After a whole design domain is divided into a set of unit modules, information on the spatiotemporal characteristics of intermediate designs and a filtering radius is used to separately predict a near-optimal design of each unit module through a trained long short-term memory (convLSTM) network. Then, in the second-stage topology optimization, a combined near-optimal design of a whole design domain is used as an initial design to determine the optimized design in a more efficient way. To train a convLSTM network, a history of intermediate designs is obtained under a randomly generated boundary condition of a unit module. The filtering radius is also used as the training data to reflect the geometric features affected by a filtering process. For four examples with different design domains and boundary conditions, the proposed method successfully provides the accelerated convergence up to 6.09 with a negligible loss of accuracy less than 1.12% error. These numerical results also demonstrate that the proposed unit module-based approach achieves a scalable convergence acceleration at a design domain of an arbitrary size (or resolution). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Unit Module-Based Convergence Acceleration for Topology Optimization Using the Spatiotemporal Deep Neural Network | - |
dc.type | Article | - |
dc.identifier.wosid | 000717769700001 | - |
dc.identifier.scopusid | 2-s2.0-85118649073 | - |
dc.type.rims | ART | - |
dc.citation.volume | 9 | - |
dc.citation.beginningpage | 149766 | - |
dc.citation.endingpage | 149779 | - |
dc.citation.publicationname | IEEE ACCESS | - |
dc.identifier.doi | 10.1109/ACCESS.2021.3125014 | - |
dc.contributor.localauthor | Jang, In Gwun | - |
dc.contributor.nonIdAuthor | Joo, Younghwan | - |
dc.contributor.nonIdAuthor | Yu, Yonggyun | - |
dc.description.isOpenAccess | Y | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Optimization | - |
dc.subject.keywordAuthor | Topology | - |
dc.subject.keywordAuthor | Network topology | - |
dc.subject.keywordAuthor | Training data | - |
dc.subject.keywordAuthor | Finite element analysis | - |
dc.subject.keywordAuthor | Filtering | - |
dc.subject.keywordAuthor | Convergence | - |
dc.subject.keywordAuthor | Convergence acceleration | - |
dc.subject.keywordAuthor | deep learning | - |
dc.subject.keywordAuthor | finite element method | - |
dc.subject.keywordAuthor | structural topology optimization | - |
dc.subject.keywordPlus | DESIGN | - |
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