Decoupled address translation architecture for heterogeneous memory systems

Abstract

The heterogeneous memory has become a promising new solution for satisfying ever growing memory capacity demands in a cost-effective way. In the heterogeneous memory, the fast and high bandwidth memory is used to store performance-critical data, while the slow and low bandwidth memory provides the capacity backup. In supporting such hybridization of memory, the virtual memory system is the key mechanism, which combines different memory components to a single memory view. However, the support for the heterogeneous memory in the conventional virtual memory has an inherent problem. With the dramatic increase of data size, data-centric application is becoming pervasive. For the efficient address translation for data-centric workloads with large footprint, translation lookaside buffers (TLBs) was introduced to conventional systems. Since TLBs cache address mappings on page granularity, the page size has been growing to increase coverage of address translation. However, the heterogeneous memory support requires the fine-grained migration mapping to store only necessary portions of the memory in the precious fast memory. Coarse-grained large page reduces efficiency of heterogeneous memory and causes the severe migration cost. To address the challenges posed by the conflicting goals in the heterogeneous memory support, this paper proposes to decouple the address translation into a two-step process. The decoupling resolves the conflict as the critical core-side TLBs perform the translation to an intermediate address space, and the memory-side translation provides the actual physical location of the memory devices. The first step translation provides memory capacity allocation and permission checking without considering the heterogeneity, while the second step translation enables the heterogeneity-aware page placement. In second step translation, the decoupled architecture also offers flexibility of management granularity in heterogeneous memory. By sampling-based dynamic granularity selection in memory-side, the proposed architecture has adaptive mapping granularity depending on memory usage patterns. The experimental results from multi-core simulations show that the proposed two-step memory virtualization improves the performance by 36% on average compared to the prior heterogeneous memory solution with the conventional virtual memory.