Reconfigurable DRAM cache architecture for hybrid memory systems

Abstract

The recent increasing heterogeneity in memory components has enabled a composite memory system consisting of more than two types of different memory technologies. DRAM caches have emerged as an efficient new layer in the memory hierarchy to address the increasing diversity of memory components. The other alternative is that using fast memory as a part of main memory have benefits of increasing available memory capacity. When a small and fast memory is combined with a slow but large memory, the cache-based organization of the fast memory can provide a SW-transparent solution for the hybrid memory systems. Although there have been various advancements in DRAM cache designs, the effectiveness of DRAM caches which store both tag and data in the rows of DRAM, is affected by the bandwidth and latency of both fast and slow memory in addition to the memory access patterns of applications.

In this dissertation first investigates how prior approaches perform with diverse hybrid memory configurations to quantitatively assess the effect of memory configurations and application patterns on the DRAM cache designs. From the investigation, we observe no single DRAM cache organization always outperforms the other organizations across all the hybrid memory configurations and workload patterns. Based on the observation, we proposes a reconfigurable DRAM cache design which can adapt to different HW configurations and application patterns. Unlike the fixed tag and data arrays of conventional on-chip SRAM caches, this study advocates to exploit the flexibility of DRAM caches, which can store tags and data to DRAM in any arbitrary way. Using a sample-based mechanism, the proposed DRAM cache controller dynamically finds the best organization from candidates and applies the best one by reconfiguring the tags and data in the DRAM cache. We have explored the potential overhead of the reconfiguration process, and devised mechanism to optimize for this cost. This dissertation also studies the performance effectiveness of using fast memory as part of main memory in the hybrid memory system. Despite many prior studies on architecture in hybrid memory systems, the advantages of different hybrid memory managing techniques have not been investigated thoroughly. To solve the limitation of efficient hybrid memory configurations for each mode, we propose a resizable DRAM cache in the hybrid memory system. Our evaluation shows that the proposed scheme can outperform the fixed configurations across diverse hybrid memory configurations.