Circuit timing optimization through selective use of airgap IMD

Abstract

Airgap inter-metal dielectric refers to an intentional void used with some dielectric material, which brings about reduction in coupling capacitance due to reduced inter-metal dielectric permitivity. We address three key problems in circuit timing optimization using airgap inter-metal dielectric. First, we present circuit timing optimization in the limited number of airgap layers that employ airgap inter-metal dielectric, where the airgap layers that maximize total negative slack for setup are selected and the wires that constitute timing critical paths but are not on airgap layers are selectively reassigned to airgap layers to further improve total negative slack. Next, we propose an algorithm for clock tree optimization through selective airgap insertion. Given a circuit after clock tree synthesis and clock tree optimization, it determines the amount of airgap for each clock wire to mimize clock skew and power consumption. Finally, automatic airgap insertion taking into account of design rules is addressed, which realizes feasible airgap mask by respecting the timing optimization results.