(A) strategy for optimizing low operating voltage in a gate-less and capacitor-less silicon biristor

Abstract

A pure silicon-based biristor with low latch-up voltage operation and wide latch window was studied using numerical simulations. Various parameters were optimized, including the doping concentrations of the emitter, base and collector as well as the geometric dimensions of the base length and base diameter. An optimization methodology that considers the physical influences of each parameter mentioned above can provide insightful guidance for actual device fabrication. A pure silicon biristor with both low operating voltage and a wide sensing window, without capacitor, gate and gate insulator, can be applied for post-DRAM technology.