Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments

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Static random-access memory-based field-programmable gate arrays are increasingly being used for on-board processors in space missions. However, they are very susceptible to single event upsets that can generate on-board processor system malfunction or system failures in space radiation environments. This paper presents an on-board processor system adopting Triple Modular Redundancy with the concept of mitigation windows and external scrubber, and then suggests a mathematical model that predicts the on-board processor system failure rate by only using the information of system configuration resources. Our mathematical derivation can estimate on-board processor system reliability as a function of the single event upset rate, the number of mitigation windows, and on-board processor shield thickness. In addition, a guideline of the on-board processor system design is provided for achieving good single event upset mitigation capability and system reliability.
Publisher
ELSEVIER SCI LTD
Issue Date
2019-03
Language
English
Article Type
Article
Citation

RELIABILITY ENGINEERING & SYSTEM SAFETY, v.183, pp.374 - 386

ISSN
0951-8320
DOI
10.1016/j.ress.2018.09.015
URI
http://hdl.handle.net/10203/280861
Appears in Collection
AE-Journal Papers(저널논문)
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