DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Seunghwa | ko |
dc.contributor.author | Choi, Jihwan P. | ko |
dc.date.accessioned | 2021-02-18T09:10:11Z | - |
dc.date.available | 2021-02-18T09:10:11Z | - |
dc.date.created | 2021-02-18 | - |
dc.date.issued | 2019-03 | - |
dc.identifier.citation | RELIABILITY ENGINEERING & SYSTEM SAFETY, v.183, pp.374 - 386 | - |
dc.identifier.issn | 0951-8320 | - |
dc.identifier.uri | http://hdl.handle.net/10203/280861 | - |
dc.description.abstract | Static random-access memory-based field-programmable gate arrays are increasingly being used for on-board processors in space missions. However, they are very susceptible to single event upsets that can generate on-board processor system malfunction or system failures in space radiation environments. This paper presents an on-board processor system adopting Triple Modular Redundancy with the concept of mitigation windows and external scrubber, and then suggests a mathematical model that predicts the on-board processor system failure rate by only using the information of system configuration resources. Our mathematical derivation can estimate on-board processor system reliability as a function of the single event upset rate, the number of mitigation windows, and on-board processor shield thickness. In addition, a guideline of the on-board processor system design is provided for achieving good single event upset mitigation capability and system reliability. | - |
dc.language | English | - |
dc.publisher | ELSEVIER SCI LTD | - |
dc.title | Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments | - |
dc.type | Article | - |
dc.identifier.wosid | 000455693700028 | - |
dc.identifier.scopusid | 2-s2.0-85057611786 | - |
dc.type.rims | ART | - |
dc.citation.volume | 183 | - |
dc.citation.beginningpage | 374 | - |
dc.citation.endingpage | 386 | - |
dc.citation.publicationname | RELIABILITY ENGINEERING & SYSTEM SAFETY | - |
dc.identifier.doi | 10.1016/j.ress.2018.09.015 | - |
dc.contributor.localauthor | Choi, Jihwan P. | - |
dc.contributor.nonIdAuthor | Jung, Seunghwa | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | SRAM | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | Single event upset | - |
dc.subject.keywordAuthor | On-board processor | - |
dc.subject.keywordAuthor | System failure rate | - |
dc.subject.keywordAuthor | Reliability | - |
dc.subject.keywordPlus | SEU | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SINGLE | - |
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