Compact modeling of extremely scaled graphene FETs

Abstract

In this work, compact current modeling of field-effect transistors (FETs) with transferred graphene channel grown by using chemical vapor deposition is presented. A highly-doped silicon substrate is used as a back gate, channels are defined by using electron-beam lithography, and the channel length of the transistor is scaled down to 20 nm. The DC characteristics of the scaled graphene transistors are observed by considering the source/drain series resistances. In compact modeling of graphene FETs, an electron-hole puddle existing near the charge-neutral region (Dirac point) is considered at a low carrier density while the velocity saturation effect due to surface polar phonon scattering is included at a high carrier density.