A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop

Abstract

In this paper, we present a supply noise insensitive phase-locked loop using a wideband noise suppression loop around the oscillator. The proposed approach suppresses supply noise without reducing the voltage headroom of the oscillator and does not require any calibration or additional settling time for noise suppression. The proposed PLL is implemented in 65nm CMOS, achieving an average spur suppression of 30dB near PLL loop bandwidth, while consuming 2.73mW at the 3.2GHz output.