DC Field | Value | Language |
---|---|---|
dc.contributor.author | KIM, DONGIN | ko |
dc.contributor.author | Cho, SeongHwan | ko |
dc.date.accessioned | 2020-11-30T07:30:36Z | - |
dc.date.available | 2020-11-30T07:30:36Z | - |
dc.date.created | 2020-11-26 | - |
dc.date.issued | 2018-01-22 | - |
dc.identifier.citation | 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, pp.283 - 284 | - |
dc.identifier.issn | 2153-6961 | - |
dc.identifier.uri | http://hdl.handle.net/10203/277744 | - |
dc.description.abstract | In this paper, we present a supply noise insensitive phase-locked loop using a wideband noise suppression loop around the oscillator. The proposed approach suppresses supply noise without reducing the voltage headroom of the oscillator and does not require any calibration or additional settling time for noise suppression. The proposed PLL is implemented in 65nm CMOS, achieving an average spur suppression of 30dB near PLL loop bandwidth, while consuming 2.73mW at the 3.2GHz output. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop | - |
dc.type | Conference | - |
dc.identifier.wosid | 000426987100048 | - |
dc.identifier.scopusid | 2-s2.0-85045327108 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 283 | - |
dc.citation.endingpage | 284 | - |
dc.citation.publicationname | 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 | - |
dc.identifier.conferencecountry | KO | - |
dc.identifier.conferencelocation | International Convention Center Jeju | - |
dc.identifier.doi | 10.1109/ASPDAC.2018.8297321 | - |
dc.contributor.localauthor | Cho, SeongHwan | - |
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