DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Hongkeun | ko |
dc.contributor.author | Yoo, Hocheon | ko |
dc.contributor.author | Lee, Chungryeol | ko |
dc.contributor.author | Kim, Jae-Joon | ko |
dc.contributor.author | Im, Sung Gap | ko |
dc.date.accessioned | 2020-11-30T07:30:07Z | - |
dc.date.available | 2020-11-30T07:30:07Z | - |
dc.date.created | 2020-10-22 | - |
dc.date.created | 2020-10-22 | - |
dc.date.created | 2020-10-22 | - |
dc.date.created | 2020-10-22 | - |
dc.date.issued | 2020-11 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.41, no.11, pp.1685 - 1687 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/277740 | - |
dc.description.abstract | Multi-metal interconnection is a crucial technology for the development of large-scale integrated circuits (ICs). However, organic semiconductors are not robust enough to be compatible with conventional lithography-and-etching-based via-forming methods. Thus, an alternative metal interconnect method is required for successful organic IC implementation. In-situ patterning of a dielectric polymer through a shadow mask while depositing in vapor phase possibly addresses the issues in both solvent susceptibility and process complexity. Here we report multi-stage organic logic circuits with a multi-level metal interconnection scheme based on patterned interlayer dielectrics via vapor phase deposition. We implement an exclusive OR circuit composed of four 2-input NAND gates and three-level metal interconnections to demonstrate the potential of the proposed solvent-free metal interconnection scheme. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects | - |
dc.type | Article | - |
dc.identifier.wosid | 000584248800018 | - |
dc.identifier.scopusid | 2-s2.0-85094882638 | - |
dc.type.rims | ART | - |
dc.citation.volume | 41 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 1685 | - |
dc.citation.endingpage | 1687 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/led.2020.3027423 | - |
dc.contributor.localauthor | Im, Sung Gap | - |
dc.contributor.nonIdAuthor | Yoo, Hocheon | - |
dc.contributor.nonIdAuthor | Kim, Jae-Joon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Integrated circuit interconnections | - |
dc.subject.keywordAuthor | Metals | - |
dc.subject.keywordAuthor | Inverters | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | Organic thin film transistors | - |
dc.subject.keywordAuthor | Organic semiconductors | - |
dc.subject.keywordAuthor | interconnection | - |
dc.subject.keywordAuthor | thin-film transistors | - |
dc.subject.keywordAuthor | thin-film circuits | - |
dc.subject.keywordAuthor | vapor deposition | - |
dc.subject.keywordPlus | TRANSISTORS | - |
dc.subject.keywordPlus | STABILITY | - |
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