Clock tree optimization through selective airgap insertion

Abstract

Airgap refers to a void inserted in some inter metal dielectric (IMD). It brings about reduced permittivity and corresponding reduction in coupling capacitance. We address a problem of selective airgap insertion in clock wires to reduce clock skew as well as power consumption. This is performed after conventional clock tree construction and optimization, so the reduction in clock skew due to inserted airgap is additional benefit. The problem is formulated as linear programming (LP); more practical heuristic algorithm is also proposed, whose performance is comparable to LP. Experiments demonstrate 17.0% reduction in clock skew and 11.1% reduction in clock power, on average of a few test circuits in 28-nm technology.