DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Kyung Min | ko |
dc.contributor.author | Williams, R. Stanley | ko |
dc.date.accessioned | 2019-12-13T01:27:33Z | - |
dc.date.available | 2019-12-13T01:27:33Z | - |
dc.date.created | 2019-12-02 | - |
dc.date.created | 2019-12-02 | - |
dc.date.created | 2019-12-02 | - |
dc.date.created | 2019-12-02 | - |
dc.date.issued | 2019-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.66, no.11, pp.4348 - 4355 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268838 | - |
dc.description.abstract | The conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Family of Stateful Memristor Gates for Complete Cascading Logic | - |
dc.type | Article | - |
dc.identifier.wosid | 000494680200022 | - |
dc.identifier.scopusid | 2-s2.0-85072586096 | - |
dc.type.rims | ART | - |
dc.citation.volume | 66 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 4348 | - |
dc.citation.endingpage | 4355 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2019.2926811 | - |
dc.contributor.localauthor | Kim, Kyung Min | - |
dc.contributor.nonIdAuthor | Williams, R. Stanley | - |
dc.description.isOpenAccess | Y | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Logic circuits | - |
dc.subject.keywordAuthor | Logic-in-memory | - |
dc.subject.keywordAuthor | memristors | - |
dc.subject.keywordAuthor | stateful logic | - |
dc.subject.keywordPlus | OPERATIONS | - |
dc.subject.keywordPlus | DESIGN | - |
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