DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Won-ju | ko |
dc.contributor.author | Im, Kiju | ko |
dc.contributor.author | Ahn, Chang-Geun | ko |
dc.contributor.author | Yang, Jong-Heon | ko |
dc.contributor.author | Oh, Jihun | ko |
dc.contributor.author | Baek, In-Bok | ko |
dc.contributor.author | Lee, Seongjae | ko |
dc.date.accessioned | 2019-11-07T01:20:18Z | - |
dc.date.available | 2019-11-07T01:20:18Z | - |
dc.date.created | 2019-11-05 | - |
dc.date.created | 2019-11-05 | - |
dc.date.issued | 2004-11 | - |
dc.identifier.citation | Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, v.22, no.6, pp.3210 - 3213 | - |
dc.identifier.issn | 1071-1023 | - |
dc.identifier.uri | http://hdl.handle.net/10203/268220 | - |
dc.description.abstract | We developed a plasma doping (PLAD) technique which is appropriate for the nanoscale metal-oxide-semiconductor field effect transistors (MOSFETs) fabrications. Silicon-on-insulator (SOI) n-MOSFETs with a 50-nm-length metal gate and a 100-nm-channel width were successfully fabricated. The source and drain extensions (SDE) of SOI n-MOSFETs were formed using a plasma doping technique. The advantage of this process is the exclusion of additional activation annealing after introduction of impurity in SDE, which resulted in a laterally abrupt source/drain (S/D) junction profile. We can obtain a low sheet resistance by the PLAD technique and low damaged shallow junctions. A trigate structure SOI n-MOSFET with a gate length of 50 nm fabricated by high-temperature plasma doping revealed suppressed short-channel effects. (C) 2004 American Vacuum Society. | - |
dc.language | English | - |
dc.publisher | American Institute of Physics | - |
dc.title | Plasma doping technology for fabrication of nanoscale metal-oxide-semiconductor devices | - |
dc.type | Article | - |
dc.identifier.wosid | 000226439800123 | - |
dc.identifier.scopusid | 2-s2.0-13244267391 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 3210 | - |
dc.citation.endingpage | 3213 | - |
dc.citation.publicationname | Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures | - |
dc.identifier.doi | 10.1116/1.1813461 | - |
dc.contributor.localauthor | Oh, Jihun | - |
dc.contributor.nonIdAuthor | Cho, Won-ju | - |
dc.contributor.nonIdAuthor | Im, Kiju | - |
dc.contributor.nonIdAuthor | Ahn, Chang-Geun | - |
dc.contributor.nonIdAuthor | Yang, Jong-Heon | - |
dc.contributor.nonIdAuthor | Baek, In-Bok | - |
dc.contributor.nonIdAuthor | Lee, Seongjae | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordPlus | SOI MOSFETS | - |
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