(A) data jitter tolerant low-power clock and data recovery with super-harmonic injection-locking

Abstract

therefore techniques for low power design must be discussed to maintain the benefit of the data edge injection at high data rate.

To implement the power-efficient injection-type CDR, this thesis presents two low power design techniques: source follower based edge detector and quarter-rate clocking with super-harmonic injection-locking. The proposed source follower based edge detector replaces power hungry current mode logic (CML) XOR gate and eliminates delay buffer stage in conventional edge detector. The design of the proposed edge detector is discussed by quantitative analysis. The proposed quarter-rate data-edge injection architecture with super-harmonic injection-locking enables CMOS design of oscillator and quarter-rate architecture.

The proposed injection-type CDR designed in 65nm CMOS process and operates at 10Gbps. The operation of the proposed injection-type CDR and the jitter tolerance improvement are verified by post-layout simulation. Proposed receiver achieves 1.58pJ/bit power efficiency.

As the process node scales down, computing speed of digital processor is keep increasing. The advent of virtual reality (VR) technology and cloud computing accelerates the overall system’s I/O bandwidth requirement. In consumer electronic serial link, which focuses the data recovery, data jitter tolerant link design is required in addition to high data rate and low power design.

The previous injection-type CDR, which accomplishes large jitter tolerance (JTOL) by injecting the data edge, is good candidate for consumer electronics serial link because it’s low-power consumption and good data recovery ability. The jitter tolerance improvement with low power consumption was achieved by the all-CMOS implementation of the CDR core. However, as the demand for data rate per pin rises, the power overhead of injection-locking in reference-less CDR significantly increases. The CMOS implementation is limited by the speed limit of the given CMOS process

therefore, when the data rate is above the speed limit of CMOS implementation the circuits should be design by CML. The power overhead issue arises from the CML design of the additional blocks for data edge injection