Algorithms and VLSI architectures for detection and decoding in MIMO receivers

Abstract

The multiple-input multiple-output (MIMO) and error-correcting codes (ECCs) are the most widely employed technologies in contemporary wireless communication systems for high data transfer rate and data integrity. In exchange for such benefits, complicated signal processing, i.e., MIMO detection and ECC decoding, needs to be performed in the receiver of the system. For efficient realization of the MIMO receivers, this dissertation presents several algorithmic and hardware-architectural improvements associated with detection and decoding techniques. First of all, the metrics in MIMO detection are transformed to maximize common subexpressions that can be shared. As a result, the number of operators required to compute the metrics is significantly reduced without any increase of bit-error rate. In addition, a new metric is proposed for detection in spatial modulation MIMO. The proposed metric takes into account not only the cost of the preceding path but also the estimated cost of the sub-tree that has not been visited yet. Consequently, the number of visits that crucially influences the latency is remarkably reduced. Moreover, the metric-sorting architecture for K-best MIMO detection is simplified by exploiting two properties of the metrics. The proposed simplifications lower not only the hardware complexity but also the latency. Furthermore, an efficient metric-sorting architecture is presented for successive cancellation list decoding (SCLD) of polar codes. The proposed architecture separately processes the sorted metrics and unsorted ones, and adopts the odd-even sort network as a basic building block. On average, the proposed architecture requires less than 50% of compare-and-swap units demanded by the area-efficient sorting networks in the literature. Another metric-sorting architecture is also presented for low-latency SCLD of polar codes. It hybridizes bitonic and odd-even sorts to parallelize the dataflow of SCLD. As a result, the proposed architecture not only diminishes the latency of SCLD, but also attains the hardware complexity as low as that of the state-of-the-art work. Lastly, a low-complexity detection algorithm is proposed for massive MIMO uplink. In the proposed scheme, the Jacobi method is exploited to circumvent the computationally intensive matrix inversion. In addition, a multiplication-free initial estimate for the Jacobi method is proposed to lessen the computational complexity further. The proposed algorithm achieves a near-optimal error-rate with fewer computations than the state-of-the-art schemes.