Readout circuits that compensate for temperature or temporal drift effects of the phase-change memory

Abstract

At first, this paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 μm-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 W at 13 Mcells/sec conversion rate at 1.2 V supply. Next, this paper presents a reference-free readout method for phase change memory (PCM) that compensates for the temperature drift of the cell resistance. The proposed method reconfigures the sense amplifier array into flash ADCs in order to extract the optimum decision threshold for the given temperature from the distribution of the data output therefrom. The resolution of the reconfigured flash ADC, the number of flash ADCs for data averaging, and the required number of samples are determined for a target bit-error rate of 1ppm. The proposed sense amplifier (SA) drives a bit-line (BL) rapidly with switchable current sources. A proof-of-concept prototype chip is fabricated via the 180nm CMOS process. A single-channel readout path occupies 137 x 27 $μm^2$ and consumes 305μW under a 3.3V supply, with readout latency less than 100ns.