Memory system architecture to improve data reliability of high-capacity main memory

Abstract

In recent server systems and user computing systems, it is required to process tremendous amounts of data generated by various mobile and IoT devises. In the current processor-memory based system environment, the operating data in the storage device is allocated to the memory, the processor exchanges data with the memory, and processes the tasks requested by the user. If there is not enough memory space in the process, space allocated to new data can be secured by sending the previously allocated data that is not used recently to the disk again. Accessing the storage device in this series of processes leads to a lot of latency and is a major cause of system performance degradation. Therefore, to improve system performance, it is necessary to minimize access to storage devices with long latency. The application of high capacity memory systems is a very effective way of minimizing access to storage devices, and many system manufacturers are equipped with high capacity memory when configuring high performance computing systems. DRAM, a key component of the memory system, has been increasing in capacity with the development of other components of the computing system. However, DRAM capacity growth is stalling due to scaling limitations in process technology. Even if a high-capacity DRAM is produced, it is difficult to expect an explosive capacity increase. Therefore, PCM is expected to be a next-generation memory that can replace DRAM or be combined with DRAM. However, to commercialize PCM, problems such as wear-leveling and write disturbance must be solved first. Finally, for the application of high-capacity memory systems, it is necessary to solve the factors that impede the increase of DRAM capacity and the commercialization of PCM. The main reason for hindering DRAM capacity growth is an increase in DRAM refresh cost. The DRAM must perform a refresh operation periodically because of the volatility characteristic of the cell. However, as the capacity increases, the refresh cost of the DRAM increases. Increasing the refresh period may be an effective way to reduce this cost. In the DRAM, most of the strong cells and a few weak cells are present. The charge retention time of a few weak cells determines the refresh period of the entire DRAM. The factors affecting the charge retention time of the DRAM cell are the leakage current of the cell and the reduction of the charging capability of the cell. Scaling of the process technology provides a high capacity while this gain is obtained in exchange for the reduction in the drivability of the cell by increasing the series resistance of the reduced transistor. The degraded driving capability slows down the process of charging and restoring the charge to the cell, which ultimately prevents the cell from having sufficient charge within a given time. DRAM operations require recovery processes because of the destructive nature of the cell. Among such operations, the write recovery process is most difficult to satisfy timing constraints. Therefore, in this dissertation, we intend to improve the DRAM refresh cycle by improving the charge amount in the DRAM write restoration process. To this end, the relationship between the charging time and the refresh cycle is modeled through circuit simulation. The refresh frequency can be reduced by using the relationship obtained through modeling. In addition, the performance reduction caused by the increase of the write recovery time is minimized by applying the scheduling technique using the refresh wait time. PCM has a read latency similar to that of DRAM and has higher write latency than NAND, so it is expected as next generation memory. However, crucial problems in the writing process must be solved to ensure the reliability of the PCM. One of them is the write disturbance problem. In PCM, repeated writes destroy data in neighboring cells. The number of times this occurs depends on the manufacturer, but it can occur even if the writing is repeated several thousand times. This can be solved by a scrubbing operation similar in concept to the DRAM refresh operation. However, considering the high capacity of PCM, the cost of writing by scrubbing exceeds the original number of writing. Therefore, in this dissertation, we propose an architectural technique using write private cache to solve the write disturbance problem of PCM at low cost. The proposed idea has a relatively low-capacity write private cache, and uses a random probability cache insertion policy to distribute the writes that are concentrated at a particular address of the PCM to the cache. In addition, by applying a write private cache, the durability of the PCM can be expected to be improved due to the reduction of the total number of write operations applied to the PCM. In summary, this dissertation proposes an architectural technique that analyzes and exploits the physical phenomena of memory media in order to solve the problem of increase of refresh cost in high capacity DRAM and the problem of write disturbance in PCM. The comprehensive goal of this dissertation is to visualize the possibility of using a high capacity memory system by improving the characteristics of memory media. We will show improvement of memory system performance, energy reduction, and reliability by improving characteristics of memory media. Through the system simulation, we show the benefits of the proposed techniques quantitatively, and derive the meaningful architectural conclusions through the analysis of the simulation results.