(An) input data and clock jitter tolerant digital CDR for LCD intra-panel interface

Abstract

The liquid crystal display (LCD) intra-panel interfaces should support the requirements of the high display resolution, the large color depth, and the high frame rate between the timing controller (TCON) and source driver ICs (SDICs). As the demands for the full-high-definition (FHD) is replaced by the ultra-high-definition (UHD), 4 K x 2 K (4096 x 2048) resolution is needed. The 8 bits of color depth per R/G/B color are changed to the 10 bits of color depth for many impressions of the color. The main stream of the frame rate for the UHDTV is 120 Hz for the high picture quality. Thus, the 31 Gb/s data transmission is required between timing controller and SDICs for the UHDTV. The intra-panel interfaces are composed of a TCON PCB, flexible flat cables (FFC), a source PCB, and films with point-to-point topology between timing controller and source driver ICs. By increasing the number of the interface lines per SDIC, the data rate of each SDIC decreases, but the cost of the number of the channels and pins of SDICs increases. Hence, it is beneficial as the transmission capacity of the links of the SDIC is large to reduce the cost. As a result, the data rate of the intra-panel interfaces should increase, and the clock and data recovery (CDR) suffers seriously from input data jitter because one unit interval (UI) decreases. In addition, the ground plane of the CDR is connected to that of the driver control logic (DCL) in the SDIC and to that of the LCD drivers through PCB due to the cost issue. The switching noise (SN) generated from the DCL and many LCD drivers which operate with high supply voltage induces large clock jitter (JCK) in the CDR. Thus, input data and clock jitter (IDCJ) degrade BER performance of the CDR. To increase input jitter tolerance of the CDR, the delay locked loop (DLL)-based CDR has been used because of the large jitter tracking bandwidth. However, it requires that the repeated clock information is embedded in the data stream. The repeated pattern causes electromagnetic interference (EMI). In addition, to extract the clock information from input data with the process, voltage, and temperature variations, the embedded number of bits should be at least more than 2 bits. Moreover, as the data rate increases, the channel (TCON PCB + FFC + source PCB + film) loss of the intra-panel interfaces become seriously severe. Inter-symbol interference (ISI) from the channel loss induces the data dependent jitter (DDJ). However, the DLL-based CDR cannot filter the DDJ due to wide jitter transfer characteristics. The phase-locked loop (PLL)-based CDR extracts clock information when the data transition exists. Thus, the scrambling data or balance code like 8B/10B can be used for the PLL-based CDR to be tolerant with EMI issue. Additionally, the PLL-based CDR can filter the DDJ. Hence, as the data rate increases, the PLL-based CDR is suitable for the intra-panel interfaces. To protect CDR performance from SN, a regulator with the wide bandwidth can be used. However, the bulky output capacitor of the regulator restricts full integration. In addition, the considerable drop-out voltage incurs large power for the entire CDR, and it limits scaling of the supply voltage of the SDIC due to the voltage headroom. Therefore, to ease the regulator overhead, the regulator was used only for the oscillator, but remaining blocks still suffer from SN leading to large clock jitter. In this paper, we propose a phase-locked loop (PLL)-based digital CDR including a data recovery unit (DRU) which utilizes half-bit previous data (HBPD) with a feed forward method (FFM). Previously, the FFM has been used with i-bit previous or next data to compensate for the ISI where i is the integer value. However, we observed that the HBPD with FFM can be used to improve jitter tolerance (JTOL) for IDCJ. To make the HBPD be useful signals to be added to current data, clock early/late (E/L) information are additionally needed, but they can be easily obtained from the CDR. Two prototypes are tested with half-rate clocking at 5 Gb/s data rate, and quarter-late clocking at 10 Gb/s data rate. Both 5 Gb/s and 10 Gb/s prototypes improve the tolerance of the input jitter and power noise. Fabricated in 65 nm CMOS technology, the test chips consume 17.44 mW and 20.7 mW, respectively. To enhance the performance of the proposed DRU with HBPD FFM in respect of the SNR and power efficiency, a data and edge interpolator (EDI) block is introduced for the reference-less CDR. The DEI operates as DRU with HBPD FFM for transition input data pattern to be robust to the IDCJ. For non-transition input data pattern, it enhances SNR compared to the DRU with HBPD FFM. In addition, the DRU is merged into a bang-bang phase detector to reduce the power consumption. Fabricated in 65 nm CMOS technology, the test chip consumes 8.67 mW at 9 Gb/s. As the data rate increases, an equalizer block is required to remove DDJ in the receiver. This dissertation presents adaptive continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of 1-tap DFE. Thus, adaptation loops (ALs) for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip operates 21 Gb/s and consumes 34.2 mW from 1.2 V supply with 65 nm CMOS process.