DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Kim, Mina | ko |
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-08-08T01:20:08Z | - |
dc.date.available | 2019-08-08T01:20:08Z | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.issued | 2015-03 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.3, pp.635 - 644 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/264107 | - |
dc.description.abstract | A low phase noise injection-locked reference clock multiplier that can suppress the delta-sigma (Delta Sigma) noise of Delta Sigma phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of the calibration method utilizing two identical oscillators, the self-injection pulse generator that balances the loadings of two oscillators is proposed. In addition, this work presents a systematic design methodology that minimizes the degradation of the phase noise over the PVT variations, based on the phase noise analysis of injection-locking. The clock multiplier was designed with the prototype Delta Sigma PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was -130.0 and -131.8 dBc/Hz at 100 kHz and 1 MHz offsets, respectively; the performance of low phase noise was confirmed over temperature variations. The total active area was 0.062 mm2, and the power consumption was 1.6-1.9 mW. By switching the reference frequency from 19.2 to 96 MHz, the phase noise of the prototype PLL at the 10-MHz offset from the 4.4-GHz signal was improved from -120.1 to -138.6 dBc/Hz. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for Delta Sigma PLLs | - |
dc.type | Article | - |
dc.identifier.wosid | 000350799100003 | - |
dc.identifier.scopusid | 2-s2.0-85027930471 | - |
dc.type.rims | ART | - |
dc.citation.volume | 62 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 635 | - |
dc.citation.endingpage | 644 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2014.2370191 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Kim, Mina | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | clock multiplier | - |
dc.subject.keywordAuthor | injection-locked | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | PVT | - |
dc.subject.keywordAuthor | Delta Sigma PLL | - |
dc.subject.keywordPlus | FRACTIONAL-N PLL | - |
dc.subject.keywordPlus | RING OSCILLATOR | - |
dc.subject.keywordPlus | FREQUENCY | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | DLL | - |
dc.subject.keywordPlus | LOCKING | - |
dc.subject.keywordPlus | WAVE | - |
dc.subject.keywordPlus | VCO | - |
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