DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Seojin | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Lim, Younghyun | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-08-08T00:20:14Z | - |
dc.date.available | 2019-08-08T00:20:14Z | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1878 - 1889 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/264101 | - |
dc.description.abstract | A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was 0.06 mm(2) and total power consumption was 9.5 mW. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector | - |
dc.type | Article | - |
dc.identifier.wosid | 000382169400013 | - |
dc.identifier.scopusid | 2-s2.0-84976271612 | - |
dc.type.rims | ART | - |
dc.citation.volume | 51 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 1878 | - |
dc.citation.endingpage | 1889 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2016.2574804 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Choi, Seojin | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.contributor.nonIdAuthor | Lim, Younghyun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Calibrator | - |
dc.subject.keywordAuthor | clock multiplier | - |
dc.subject.keywordAuthor | frequency-tracking loop (FTL) | - |
dc.subject.keywordAuthor | injection-locked | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | process-voltage-temperature (PVT) | - |
dc.subject.keywordAuthor | real-time | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordPlus | CALIBRATION | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | LOCKING | - |
dc.subject.keywordPlus | DESIGN | - |
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