DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-08-07T08:20:04Z | - |
dc.date.available | 2019-08-07T08:20:04Z | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.created | 2019-08-07 | - |
dc.date.issued | 2018-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1192 - 1202 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/264085 | - |
dc.description.abstract | A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and -71 dBc, respectively. The total active area was 0.047 mm(2), and the power consumption was 4.6 mW. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000428676100023 | - |
dc.identifier.scopusid | 2-s2.0-85035080965 | - |
dc.type.rims | ART | - |
dc.citation.volume | 53 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 1192 | - |
dc.citation.endingpage | 1202 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2017.2768411 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | multiplication factor | - |
dc.subject.keywordAuthor | phase-error correction | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | reference spur | - |
dc.subject.keywordAuthor | ring voltage-controlled oscillator (VCO) | - |
dc.subject.keywordAuthor | switched-loop filter (SLF) | - |
dc.subject.keywordPlus | CLOCK MULTIPLIER | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | OSCILLATOR | - |
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