One of the key technologies for developing 3-D Packaging with vertical interconnection is the interlayer metallization using formation and filling of through silicon vias. We deal with filling of via holes with diameters of 5.4-7.5 mum and depths of 47-60 mum using Cu electroplating. Prior to electroplating, the interior regions of the via holes are needed to be coated with Cu layer as a seed layer for the subsequent Cu electroplating process. In this work, Cu thin layers are deposited by using ionized metal plasma (IMP) sputtering. The IMP sputtering enables more conformal deposition of Cu seed layer on the sidewall of the via holes than conventional sputtering. And it is more cost-effective than chemical vapor deposition. Deposition profiles of Cu seed layers inside the via holes are closely examined by measuring X-ray intensity ratios of Cu La to Si Ka as a function of substrate bias power. The via holes coated with Cu seed layers are then filled with Cu electroplating. We study the effects of the deposition profiles of Cu seed layers on the filling of electroplated Cu for the via holes.