High-Performance InAs-On-Insulator n-MOSFETs With Ni-InGaAs S/D Realized by Contact Resistance Reduction Technology

Abstract

We have systematically analyzed the components of source/drain (S/D) resistance (R-SD) in InGaAs n-MOSFETs with Ni-InGaAs metal S/D. It is found that Ni-InGaAs has a low resistivity of similar to 250 mu Omega.cm in a thickness of Ni-InGaAs (TNi-InGaAs) of down to similar to 4 nm. Contact resistance between the contact pads and Ni-InGaAs (R-C) is found to be the most dominant component of R-SD in control InGaAs MOSFETs, because of the existence of Ni oxides. By developing a surface cleaning process using NH4OH and H-2 plasma for Ni-InGaAs surfaces, we have reduced R-C down to 11 Omega.mu m without any accompanying drawbacks. Also, the increase in the channel indium (In) content has provided further R-SD reduction. Employing these R-SD reduction technologies, we present 20-nm-channel length (L-ch) InAs-on-insulator n-MOSFETs on Si substrates with Ni-InGaAs metal S/D. The devices provide a high maximum ON-current (I-ON) and maximum transconductance (G(m)) of 2.38 mA/mu m and 1.95 mS/mu m at drain voltage (V-D) of 0.5 V. This high performance is attributable to the low R-SD realized by the surface cleaning process of Ni-InGaAs surfaces before the contact pad formation as well as the increase in the In content in the channel layer. Furthermore, it is found that the interface resistance (R-interface) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Omega.mu m by increasing the In content in the channel layers.