A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems

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This paper present an energy-efficient block-concatenated BCH (BC-BCH) decoder which can achieve superior decoding performance for NAND flash storage systems. To enhance the error-correcting capability, an additional decoding step with single parity-check (SPC) block is newly employed. A novel memory based syndrome updating method effectively improves the energy efficiency as well as the decoding latency. Using the proposed methods, a prototype chip is implemented to decode a (36443, 32768) BC-BCH code in 65nm CMOS process. The proposed decoder provides a decoding throughput of 6.37Gb/s and an efficiency of 2.4pJ/bit, being superior to the state-of-the-art hard-decision decoders for storages.
Publisher
IEEE
Issue Date
2018-01
Language
English
Citation

23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.329 - 330

DOI
10.1109/ASPDAC.2018.8297344
URI
http://hdl.handle.net/10203/243968
Appears in Collection
EE-Conference Papers(학술회의논문)
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