(A) low-reference spur MDLL-based clock multiplier and derivation of discrete-time noise transfer function for phase noise analysis

Abstract

A MDLL-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a PLL mode to align the coarse phase and a MDLL mode to obtain a delay-lock. With non-overlap dual PD pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line (MDL) from that of delay line (DL). The NTF includes aliasing effect and shows better accuracy than the prior VCO realignment based approaches. This clock multiplier occupies an active area of 0.047 $mm^2$ in 40 nm CMOS process. The clock multiplication ratio (N) is an integer value from 8 to 27. With a low-cost 19.2 MHz TCXO reference, 153.6-518.4 MHz clocks were successfully generated, and a phase noise of -124 dBc/Hz at 100 kHz offset from a 518.4 MHz clock, RMS jitter of 1.28 ps, and -65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 V and 1.1 V supplies.