DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Kwy Ro | - |
dc.contributor.advisor | 이귀로 | - |
dc.contributor.author | Tak, Geum-Young | - |
dc.contributor.author | 탁금영 | - |
dc.date.accessioned | 2018-05-23T19:38:13Z | - |
dc.date.available | 2018-05-23T19:38:13Z | - |
dc.date.issued | 2017 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=718943&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/242068 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2017.8,[iv, 44 p. :] | - |
dc.description.abstract | A MDLL-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a PLL mode to align the coarse phase and a MDLL mode to obtain a delay-lock. With non-overlap dual PD pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line (MDL) from that of delay line (DL). The NTF includes aliasing effect and shows better accuracy than the prior VCO realignment based approaches. This clock multiplier occupies an active area of 0.047 $mm^2$ in 40 nm CMOS process. The clock multiplication ratio (N) is an integer value from 8 to 27. With a low-cost 19.2 MHz TCXO reference, 153.6-518.4 MHz clocks were successfully generated, and a phase noise of -124 dBc/Hz at 100 kHz offset from a 518.4 MHz clock, RMS jitter of 1.28 ps, and -65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 V and 1.1 V supplies. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | mdll▼anoise transfer function▼areference spur▼amismatch calibration▼adiscrete-time model | - |
dc.subject | 이산시간모델▼a불일치보정▼a배수지연고정루프▼a잡음전달함수▼a기준클럭스퍼 | - |
dc.title | (A) low-reference spur MDLL-based clock multiplier and derivation of discrete-time noise transfer function for phase noise analysis | - |
dc.title.alternative | 낮은 스퍼의 MDLL과 위상잡음 분석을 위한 이산시간 잡음전달함수의 유도 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
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