DC Field | Value | Language |
---|---|---|
dc.contributor.author | 류승탁 | ko |
dc.date.accessioned | 2017-12-21T00:53:04Z | - |
dc.date.available | 2017-12-21T00:53:04Z | - |
dc.date.issued | 2011-07-26 | - |
dc.identifier.uri | http://hdl.handle.net/10203/237055 | - |
dc.description.abstract | An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code. | - |
dc.title | Method and apparatus for digital error correction for binary successive approximation ADC | - |
dc.title.alternative | SAR ADC를 위한 디지털 에러수정기법 | - |
dc.type | Patent | - |
dc.type.rims | PAT | - |
dc.contributor.localauthor | 류승탁 | - |
dc.contributor.assignee | KAIST | - |
dc.identifier.iprsType | 특허 | - |
dc.identifier.patentApplicationNumber | 12588819 | - |
dc.identifier.patentRegistrationNumber | 07986253 | - |
dc.date.application | 2009-10-29 | - |
dc.date.registration | 2011-07-26 | - |
dc.publisher.country | US | - |
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