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Showing results 1 to 41 of 41

1	A Complete Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), 2000
2	A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), 2000
3	A New Approach to the Multiport Memory Allocation Problem in Data Path Synthesis Taewhan Kim; C.L. Liu, INTEGRATION-THE VLSI JOURNAL, v.19, no.3, pp.133 - 160, 1995-10
4	A Non-Zero Delay Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000
5	A Practical Approach to the Synthesis of Arithmetic Circuits using Carry-Save Adders Taewhan Kim; Junhyung Um, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.19, no.5, pp.615 - 624, 2000-05
6	A Scheduling Algorithm for Conditional Resource Sharing Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), pp.84 - 87, 1991
7	A Scheduling Algorithm for Conditional Resource Sharing - A Hierarchical Reduction Approach Taewhan Kim; Noritake Yonezawa; Jane W.S. Liu; C.L. Liu, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.13, no.4, pp.425 - 438, 1994-04
8	A Scheduling Strategy for Tasks with Precedence and Conditional Execution Hideroni Nakazato; Jane W. S. Liu; Taewhan Kim, TRANSACTIONS OF INFORMATION PROCESSING SOCIETY OF JAPAN, v.36, no.9, pp.2161 - 2174, 1995-09
9	A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability Taewhan Kim, IEEE European Design and Test Conference (EDAC), pp.586 - 590, 1994
10	A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.313 - 316, 2000
11	A Verification of Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000
12	Accurate Exploration of Timing and Area Trade-offs in Arithmetic Optimization using Carry-Save-Adders Youngtae Kim; Taewhan Kim, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.10, no.5, pp.279 - 292, 2001-10
13	Address Code Optimization using Code Scheduling for Digital Signal Processors Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05
14	An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.622 - 627, 2001
15	An Efficient Binding Algorithm for Power Optimization based on Network Flow Method Taewhan Kim, 6th Korea-Japan Joint Workshop on Algorithms and Computation, pp.9 - 14, 2001
16	An Efficient Data Path Synthesis Algorithm for Behavioral-level Power Optimization Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-294 - I-297, 1999
17	An Efficient Inverse Multiplier/Divider Architecture for Cryptography Systems Taewhan Kim, IEEE International Symposium on Circuits and Systems (ISCAS), 2003
18	An Efficient Low-Power Binding Algorithm in High-Level Synthesis Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05
19	An Integrated Algorithm for Incremental Data Path Synthesis Taewhan Kim; C.L. Liu, JOURNAL OF VLSI SIGNAL PROCESSING, v.12, no.3, pp.265 - 285, 1996-06
20	An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization Chaeryung Park; Taewhan Kim; C.L. Liu, VLSI DESIGN, v.11, no.4, pp.381 - 396, 2000
21	An Integrated Approach to Data Path Synthesis for Low Power Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.125 - 129, 1999
22	An Integrated Data Path Synthesis Algorithm based on Network Flow Method Taewhan Kim, IEEE Custom Integrated Circuits Conference (CICC), pp.615 - 618, 1995
23	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits Junhyung Um; Taewhan Kim, IEEE TRANSACTIONS ON COMPUTERS, v.50, no.3, pp.215 - 233, 2001-03
24	Arithmetic Optimization using Carry-Save Adders Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.442 - 447, 1998
25	Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000
26	Circuit Optimization using Carry-Save-Adder Cells Taewhan Kim; William Jao; Steve Tjiang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.17, no.10, pp.974 - 984, 1998-10
27	Comments on the Originality of the Paper, ``The Integrated Scheduling and Allocation of High-Level Test synthesis'' Taewhan Kim, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS, v.E82-A, no.12, pp.2833 - 2833, 1999-12
28	Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim; Sung-Mo Kang, ELECTRONICS LETTERS, v.37, no.13, pp.813 - 814, 2001-06
29	Domino Logic Synthesis based on Implication Graph for Set of Mandatory Assignments Ki-Wook Kim; Taewhan Kim; C.L. Liu; Sung-Mo Kang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.21, no.2, pp.232 - 240, 2002-02
30	Enhanced Bus Invert Encoding for Low-Power Taewhan Kim, IEEE International SYmposium on Circuits and Systems, 2002
31	G-Vector: A New Model for Glitch Analysis Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.159 - 162, 1999
32	Low Power Bus Encoding with Crosstalk Delay Elimination Taewhan Kim, IEEE ASIC/SOC Conference (ASIC), IEEE, 2002-09
33	Memory Exploration utilizing Scheduling Effects in High-level Synthesis Taewhan Kim, IEEE International Symposium on Circuits and Systems, IEEE, 2002-05
34	Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003
35	Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.125 - 130, 2003
36	Phase Assignment for the Synthesis of Low Power Domino Circuits Priyadasan Patra; Unni Narayanan; Taewhan Kim, ELECTRONICS LETTERS, v.37, no.13, pp.814 - 816, 2001-06
37	Power Optimization in VLSI Design based on Efficient Network Flow Computations Taewhan Kim, 6th Korea-Japan Workshop on ALgorithms and Computation, pp.3 - 8, 2001
38	Register Allocation for Dataflow Graphs with Conditional Branches and Loops Taewhan Kim, IEEE European Design Automation Conference (Euro-DAC), pp.232 - 237, 1993
39	Utilization of Carry-Save Adders in Arithmetic Optimization Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), pp.173 - 177, 1999
40	Utilization of Multiport Memories in Data Path Synthesis Taewhan Kim, ACM/IEEE Design Automation Conference (DAC), pp.298 - 302, 1993
41	Wallace-Tree based Timing-Driven Synthesis of Arithmetic Circuits Taewhan Kim, IEEE International Conference on VLSI and CAD (VLSICAD), pp.89 - 94, 1999

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