Pipeline structure of memory for high-fast row-cycle

Abstract

The present invention relates to a DRAM structure for reducing row latency for an irregular row access and for improving the effective bandwidth by varying a DRAM cell core structure, specifically, to a pipeline structure of a memory for a fast row cycle, which is different from a structure used in a conventional fast cycle RAM (FCRAM) and is established by modifying a cell core access in the channel structure of a virtual channel memory (VCM) and by introducing a row buffer and a latch to a decoder.