Pipeline structure of memory for high-fast row-cycle고속 열 사이클이 가능한 메모리의 파이프 라인 구조
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 유회준 | ko |
| dc.date.accessioned | 2017-12-20T11:16:34Z | - |
| dc.date.available | 2017-12-20T11:16:34Z | - |
| dc.date.issued | 2003-04-08 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/233742 | - |
| dc.description.abstract | The present invention relates to a DRAM structure for reducing row latency for an irregular row access and for improving the effective bandwidth by varying a DRAM cell core structure, specifically, to a pipeline structure of a memory for a fast row cycle, which is different from a structure used in a conventional fast cycle RAM (FCRAM) and is established by modifying a cell core access in the channel structure of a virtual channel memory (VCM) and by introducing a row buffer and a latch to a decoder. | - |
| dc.title | Pipeline structure of memory for high-fast row-cycle | - |
| dc.title.alternative | 고속 열 사이클이 가능한 메모리의 파이프 라인 구조 | - |
| dc.type | Patent | - |
| dc.type.rims | PAT | - |
| dc.contributor.localauthor | 유회준 | - |
| dc.contributor.assignee | KAIST | - |
| dc.identifier.iprsType | 특허 | - |
| dc.identifier.patentApplicationNumber | 09807141 | - |
| dc.identifier.patentRegistrationNumber | 6545936 | - |
| dc.date.application | 2001-04-06 | - |
| dc.date.registration | 2003-04-08 | - |
| dc.publisher.country | US | - |
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