Wafer-Level Double-Layer Nonconductive Films for Flip-Chip Assembly

Abstract

3-D chip-stacking packages and 3-D through silicon via (TSV) vertical interconnection are popular flip-chip assembly methods. Cu-pillar/SnAg micro bumps have usually been used for vertical interconnections in the 3-D TSV chip stacking. These vertical interconnections are fabricated using a thermocompression bonding method with nonconductive films (NCFs). The fabrication heat and pressure lead to molten solder wetting the pad. However, the deformed molten solder on the sidewall of the Cu-pillar results in an increase in solder and Cu-pillar contact interfaces. As a result, more Sn is consumed and Kirkendall voids occur at the solder joint. Novel double-layer NCFs (D-NCFs) can solve the problem of solder wetting the sidewall of the Cu-pillar. D-NCFs are two NCF layers, consisting of a fast-curing top NCF layer and a slower-curing bottom NCF layer. The top NCF layer is designed to have a curing onset temperature below the melting temperature of the solder, to prevent the molten solder wetting the Cu-pillar sidewall. The bottom NCF layer, which has a slower curing property and flux ability, helps the molten solder wet the pads. In this paper, D-NCFs were investigated for the wafer-level (WL) processing of 40-mu m fine-pitch Cu-pillar/SnAg micro bump chip assemblies. The D-NCFs properties were first adjusted for WL capability, and then bonding conditions were optimized in terms of solder wetting on the Cu-pillar and electrical interconnection. As a result, the D-NCFs were found to significantly increase the amount of Sn solder remaining between the Cu-pillar/SnAg/Cu interconnection, and also to decrease Sn consumption.