Refresh-Aware Write Recovery Memory Controller

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Current computer systems require large memory capacities to manage the tremendous volume of datasets. A DRAM cell consists of a transistor and a capacitor, and their size has a direct impact on DRAM density. While technology scaling can provide higher density, this benefit comes at the expense of low drivability, due to the increase in series resistance of the smaller transistor, which slows the process of restoring the charge in cells. DRAM operations require recovery processes due to the destructive nature of DRAM cells. Among such operations, the write recovery process has the most difficulty in meeting the timing constraints. In this paper, we explore an intrinsic mechanism in the DRAM write operation, and find a relation between restoration and retention times. Based on our observation, we propose a practical mechanism, Relaxed Refresh with Compensated Write Recovery (RRCW), which efficiently mitigates refresh overheads by providing longer restoration periods. Furthermore, to minimize the penalty of the longer restoration, we also introduce another mechanism, Refresh-Aware Write Recovery (RAWR), which appropriately curtails longer recovery time according to the waiting time until being refreshed. Lastly, we introduce a scheduling policy to efficiently utilize RAWR. Evaluations show that the benefits of our mechanisms increase as memory intensity increases.
Publisher
IEEE COMPUTER SOC
Issue Date
2017-04
Language
English
Article Type
Article
Keywords

LATENCY DRAM; SYSTEMS; ARCHITECTURE; PERFORMANCE

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.66, no.4, pp.688 - 701

ISSN
0018-9340
DOI
10.1109/TC.2016.2617333
URI
http://hdl.handle.net/10203/223599
Appears in Collection
EE-Journal Papers(저널논문)
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