(A) high-performance packet processing framework for heterogeneous processors

Abstract

Computer networks are evolving from fixed infrastructures into applications with multitude of features. Packet processing applications such as intrusion detection, firewalls, monitoring, and encryption have increasing demands and require continuous updates and deployments. At the past, people used expensive network equipment made of special-purpose hardware such as ASICs, but it was difficult to adapt to fluctuating traffic conditions and add new functionalities. With the advent of high-performance commodity hardware and packet I/O libraries, software-based packet processing for multi-10G environments has become feasible. Nevertheless, it remains as recurring challenges to combine and integrate them and optimize the performance for specific applications and hardware such as many-core processors (e.g., GPUs and Xeon Phi co-processors). In this thesis, we develop a packet processing framework to minimize manual performance tuning efforts. This framework embraces well-known modular abstraction from the Click modular router but hides the details of batching, pipelining, and parallelization optimized for modern hardware. Exploiting parallelism in packet processing, we also design and implement a consistent API for heterogeneous many-core processors. Moreover, our load balancing module achieves the maximum possible throughput in various workload combinations even though application developers have little knowledge on vendor-specific details of many-core processors. As the result, we show up to 80 Gbps throughput on a single x86 machine with two types of accelerators, using sample applications including IP routing and IPsec encryption gateways.