Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors

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To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs.
Publisher
IEEE COMPUTER SOC
Issue Date
2016-11
Language
English
Article Type
Article
Keywords

ENCRYPTION; ARCHITECTURE; PERFORMANCE; ATTACKS; DESIGN

Citation

IEEE TRANSACTIONS ON COMPUTERS, v.65, no.11, pp.3384 - 3397

ISSN
0018-9340
DOI
10.1109/TC.2016.2538218
URI
http://hdl.handle.net/10203/218751
Appears in Collection
CS-Journal Papers(저널논문)
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