DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jung Hoon | ko |
dc.contributor.author | Kim, Taehoon | ko |
dc.contributor.author | Huh, Jaehyuk | ko |
dc.date.accessioned | 2017-01-13T05:04:29Z | - |
dc.date.available | 2017-01-13T05:04:29Z | - |
dc.date.created | 2016-12-23 | - |
dc.date.created | 2016-12-23 | - |
dc.date.issued | 2016-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.65, no.11, pp.3384 - 3397 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/218751 | - |
dc.description.abstract | To prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.subject | ENCRYPTION | - |
dc.subject | ARCHITECTURE | - |
dc.subject | PERFORMANCE | - |
dc.subject | ATTACKS | - |
dc.subject | DESIGN | - |
dc.title | Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors | - |
dc.type | Article | - |
dc.identifier.wosid | 000388498000013 | - |
dc.identifier.scopusid | 2-s2.0-84994726547 | - |
dc.type.rims | ART | - |
dc.citation.volume | 65 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 3384 | - |
dc.citation.endingpage | 3397 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.identifier.doi | 10.1109/TC.2016.2538218 | - |
dc.contributor.localauthor | Huh, Jaehyuk | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Memory authentication | - |
dc.subject.keywordAuthor | encryption | - |
dc.subject.keywordAuthor | secure processor architecture | - |
dc.subject.keywordAuthor | memory organization | - |
dc.subject.keywordAuthor | cache management | - |
dc.subject.keywordPlus | ENCRYPTION | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | ATTACKS | - |
dc.subject.keywordPlus | DESIGN | - |
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