Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors

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dc.contributor.authorLee, Jung Hoonko
dc.contributor.authorKim, Taehoonko
dc.contributor.authorHuh, Jaehyukko
dc.date.accessioned2017-01-13T05:04:29Z-
dc.date.available2017-01-13T05:04:29Z-
dc.date.created2016-12-23-
dc.date.created2016-12-23-
dc.date.issued2016-11-
dc.identifier.citationIEEE TRANSACTIONS ON COMPUTERS, v.65, no.11, pp.3384 - 3397-
dc.identifier.issn0018-9340-
dc.identifier.urihttp://hdl.handle.net/10203/218751-
dc.description.abstractTo prevent physical attacks on systems, secure processors have been proposed to reduce trusted computing base to the processor itself. In a secure processor, all off-chip data are encrypted and their integrity is protected. This paper investigates how the limited memory bandwidth of multi-core processors affects the design of secure processors. Although the performance of a single-core secure processor has improved significantly with the counter-mode encryption combined with Bonsai Merkle Tree, our results indicate that multi-core secure processors can suffer from significant performance degradation due to the limited memory bandwidth. To mitigate the performance overheads, this paper proposes three techniques for the multi-core design of secure processors. First, the paper advocates to use a combined cache for all normal and security-supporting data. Second, the paper proposes memory scheduling and mapping schemes for secure processors. Finally, the paper investigates a type-aware cache insertion scheme considering the distinct characteristics of normal and security-supporting data. Our simulation results show that the combined techniques reduce the performance degradation for supporting full confidentiality and integrity, from 25-34 percent to less than 8-14 percent in 8-core and 16-core secure processors, with minimal extra hardware costs.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.subjectENCRYPTION-
dc.subjectARCHITECTURE-
dc.subjectPERFORMANCE-
dc.subjectATTACKS-
dc.subjectDESIGN-
dc.titleReducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors-
dc.typeArticle-
dc.identifier.wosid000388498000013-
dc.identifier.scopusid2-s2.0-84994726547-
dc.type.rimsART-
dc.citation.volume65-
dc.citation.issue11-
dc.citation.beginningpage3384-
dc.citation.endingpage3397-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPUTERS-
dc.identifier.doi10.1109/TC.2016.2538218-
dc.contributor.localauthorHuh, Jaehyuk-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorMemory authentication-
dc.subject.keywordAuthorencryption-
dc.subject.keywordAuthorsecure processor architecture-
dc.subject.keywordAuthormemory organization-
dc.subject.keywordAuthorcache management-
dc.subject.keywordPlusENCRYPTION-
dc.subject.keywordPlusARCHITECTURE-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusATTACKS-
dc.subject.keywordPlusDESIGN-
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