DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, SJ | ko |
dc.contributor.author | Kim, B | ko |
dc.contributor.author | Lee, Kwyro | ko |
dc.date.accessioned | 2011-01-27T08:52:29Z | - |
dc.date.available | 2011-01-27T08:52:29Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1997-05 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.32, no.5, pp.760 - 765 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/21867 | - |
dc.description.abstract | This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-mu m CMOS technology, To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic, The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of +/-25%. The measured frequency synthesizer performance has a frequency range from 700 kHz to 1 GHz with -80 dBc/Hz phase noise at a 100 KHz carrier offset. With an active area of 0.34 mm(2), the test chip consumes 125 mW at maximum frequency from a 5 V supply, The only external components are the supply decoupling capacitors and a passive filter. | - |
dc.description.sponsorship | The authors would like to thank LG Semicon and O. Kim in the Electronics and Telecommunications Research Institute for their fabrication support. | en |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CMOS | - |
dc.subject | CIRCUIT | - |
dc.title | A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application | - |
dc.type | Article | - |
dc.identifier.wosid | A1997WV64100018 | - |
dc.identifier.scopusid | 2-s2.0-0031145163 | - |
dc.type.rims | ART | - |
dc.citation.volume | 32 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 760 | - |
dc.citation.endingpage | 765 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, B | - |
dc.contributor.localauthor | Lee, Kwyro | - |
dc.contributor.nonIdAuthor | Lee, SJ | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | phase-locked loop | - |
dc.subject.keywordAuthor | prescaler | - |
dc.subject.keywordAuthor | voltage controlled oscillator | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordPlus | CIRCUIT | - |
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