A new efficient hold-up time compensation method for high efficiency DC/DC stage

Abstract

The conventional two-stage structured powersupply units (PSUs) requiring the hold-up time operation have generally low efficiency dc/dc stage because it is difficult to be designed optimally. As a result, to improve the efficiency of the dc/dc stage, many hold-up time compensation methods have been presented. However, they cannot still optimize the dc/dc stage due to its bad influence on the design conditions. In addition, they can only be employed in certain dc/dc topologies as well as they still ill-affect the design conditions of the dc/dc stage. Therefore, in this paper, a new hold-up time compensation method is proposed to overcome the conventional limitation. Compared to the conventional method, since the proposed method delivers the output power by using not the dc/dc stage but the power factor correction (PFC) stage during the hold-up time, it can optimize the dc/dc stage at the nominal state without any bad influence, which enables the dc/dc stage achieve a high efficiency. Furthermore, it can be widely applied to various dc/dc stages. The validity of the proposed method is confirmed by experimental results from a prototype with 90-264Vrms input and 480W/10A output.