DC Field | Value | Language |
---|---|---|
dc.contributor.author | Baek, Jae-Il | ko |
dc.contributor.author | Lee, Jae-Bum | ko |
dc.contributor.author | Youn, Han Shin | ko |
dc.contributor.author | Kang, Byunggu | ko |
dc.contributor.author | Moon, Gun-Woo | ko |
dc.contributor.author | Kim, Jae-Kuk | ko |
dc.date.accessioned | 2017-01-03T07:56:56Z | - |
dc.date.available | 2017-01-03T07:56:56Z | - |
dc.date.created | 2016-11-18 | - |
dc.date.created | 2016-11-18 | - |
dc.date.issued | 2016-05-24 | - |
dc.identifier.citation | 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), pp.2521 - 2526 | - |
dc.identifier.uri | http://hdl.handle.net/10203/215750 | - |
dc.description.abstract | The conventional two-stage structured powersupply units (PSUs) requiring the hold-up time operation have generally low efficiency dc/dc stage because it is difficult to be designed optimally. As a result, to improve the efficiency of the dc/dc stage, many hold-up time compensation methods have been presented. However, they cannot still optimize the dc/dc stage due to its bad influence on the design conditions. In addition, they can only be employed in certain dc/dc topologies as well as they still ill-affect the design conditions of the dc/dc stage. Therefore, in this paper, a new hold-up time compensation method is proposed to overcome the conventional limitation. Compared to the conventional method, since the proposed method delivers the output power by using not the dc/dc stage but the power factor correction (PFC) stage during the hold-up time, it can optimize the dc/dc stage at the nominal state without any bad influence, which enables the dc/dc stage achieve a high efficiency. Furthermore, it can be widely applied to various dc/dc stages. The validity of the proposed method is confirmed by experimental results from a prototype with 90-264Vrms input and 480W/10A output. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A new efficient hold-up time compensation method for high efficiency DC/DC stage | - |
dc.type | Conference | - |
dc.identifier.wosid | 000390949702121 | - |
dc.identifier.scopusid | 2-s2.0-84983343708 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 2521 | - |
dc.citation.endingpage | 2526 | - |
dc.citation.publicationname | 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia) | - |
dc.identifier.conferencecountry | CC | - |
dc.identifier.conferencelocation | Platinum Hanjue Hotel, Hefei | - |
dc.identifier.doi | 10.1109/IPEMC.2016.7512695 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Moon, Gun-Woo | - |
dc.contributor.nonIdAuthor | Kang, Byunggu | - |
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